The present invention relates generally to electronic circuit design and manufacturing.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
Rapid developments in the technology and equipment used to manufacture semiconductor ICs have allowed electronics manufacturers to create smaller and more densely packed chips in which the IC components, such as wires, are located very close together. When electrical components are spaced too close together, the electrical characteristics or operation of one component may affect the electrical characteristics or operation of its neighboring components. The reaction or noise that is triggered by this interference between components is called the “crosstalk” effect.
Many types of crosstalk effects may occur in a circuit. For example, if a first wire (“victim”) is supposed to be in a stable state but its neighboring wire (“aggressor”) is moving up or down, then excess interference from the aggressor wire may pull the victim wire up or down with it. If the victim wire improperly and unexpectedly leaves its stable state, this could cause the intended operation of the IC to fail. As another example, if the current in an aggressor wire is in the same direction as the current in a nearby victim wire, the resultant crosstalk may cause the victim wire to switch too quickly. On the other hand, if the current in an aggressor wire is in the opposite direction from the nearby victim wire, then the resultant crosstalk may cause the victim wire to switch too slowly. In either case, the crosstalk effect may cause the IC to fail.
Therefore, it is highly desirable to be able to obtain accurate estimates of the effects of crosstalk before finalizing the design of an IC. Delay calculations can be performed to determine whether the IC design creates excessive crosstalk that can cause the IC to fail.
One approach for handling this type of analysis is to perform a full-chip simulation. The full-chip simulation involves simulation activity that checks the performance of the entire chip and its components. While this approach may be relatively accurate, the problem with this approach is that it is normally very expensive to run a full-chip simulation given the size, complexity, and number of components on modern IC designs. Simulating an IC design having hundreds of thousands or millions of components could consume an inordinate amount of time and computing equipment. As technology progresses and the complexity and number of components increase on typical designs, this approach becomes ever more impractical.
To obtain faster analysis results, another proposed approach is to drive crosstalk analysis from a measurement of the ratio of coupled capacitance from any neighbor to total net capacitance, assuming coincident switching in opposite directions between the aggressors and the affected victim signals. Unfortunately, while this simplistic solution that may be faster than a full-chip simulation, it may also result in inaccurate approximations of the true delay characteristics of the design, since this approach only considers capacitance when determining delay. The problem is that if the delay characteristics are underestimated, then unexpected delays may cause the chip to fail. However, if the delays characteristics are overestimated, this may cause the designer to over-design the chip to address “phantom” problems that do not truly exist in the chip design.
Disclosed is an improved approach for performing crosstalk and signal integrity analysis. According to an embodiment of the invention, multiple variables are taken into account when analyzing the effects of on-chip crosstalk, such as for example coupled wire length, ration of coupling capacitance, and aggressor and victim driver types. Rather than performing a full-chip simulation, the potential crosstalk effects can be pre-characterized by performing simulation/modeling over specific net portions by systematically changing the values of these multiple variables. A set of patterns characterized from the variables are formed from the modeling. During the analysis process, the IC design is checked of the presence of the patterns, from which is produced the expected delay impact for crosstalk in the design. Other and additional objects, features, and advantages of the invention are described in the detailed description, figures, and claims.